RANDOM PROCESS VARIATIONS, CIRCUIT TIMING MARGINALITIES AND SILENT DATA ERRORS

Adit SINGH (Auburn University) 

New types of failures that escape traditional scan DFT tests are being increasingly observed in SOCs. For example, recent presentations (since 2021) from Google and Facebook (Meta) have reported significant levels of silent data corruption in their large data centers. These occasional transient failures have been associated with specific processor cores in these large processor networks, suggesting faulty or unstable hardware from test escapes rather than failures from random environmental noise. The inability of scan structural tests to detect these failures has resulted in the introduction of an entirely new function system level test (SLT) over the past few years, to serve as an additional final defect screen in manufacturing test flows. However, even these expensive functional tests allow significant test escapes that cause malfunction in operation. We explain why timing marginalities resulting from manufacturing process variations, greatly accentuated in low voltage operation, are the likely cause of much of the SLT fallout. Furthermore, these failures can even escape detection by SLT and can cause many of the silent data errors reported by datacenters. To explain this, we review scan DFT tests in depth, including recent advances such as cell aware test, path delay tests, and timing aware tests. This helps us understand why scan tests are unable to reliably detect timing errors from process variations. Finally, we present and explain research, as validated on published volume production test data from Intel’s advanced 14nm FinFET technology, which suggests ways of leveraging the voltage and timing of the applied timing tests to enhance the detection of marginal timing parts during scan and system level testing. The goal is to reliably screen out these marginal parts during postproduction testing and thereby prevent them from causing errors in operation.

Dr. Adit D. Singh is Godbold Endowed Chair Professor of Electrical and Computer Engineering at Auburn University. Before joining Auburn in 1991, he served on the faculty at the University of Massachusetts in Amherst, and Virginia Tech in Blacksburg. He has held several visiting positions during sabbaticals, including at the University of Tokyo in Japan, the Universities of Freiburg and Potsdam in Germany, the Indian Institutes of Technology, and as Fulbright Awardee at the University Polytechnic of Catalonia in Barcelona, Spain. He has also conducted over 75 tutorials and short courses at conferences, universities and industry worldwide. His technical interests span all aspects of VLSI technology, in particular integrated circuit test and reliability. He has published over two hundred and fifty research papers and holds international patents that have been licensed to industry. He is particularly recognized for his pioneering contributions to statistical methods in test and adaptive testing. He has served as a consultant to many major semiconductor, test and EDA companies around the world, including as an expert witness on patent litigation cases. He has had leadership roles as General Chair/Co-Chair/Program Chair for dozens of international VLSI design and test conferences. Most recently he was Program Co-Chair for the 2014 International Conference on VLSI Design, and Program Chair for the 2015 Asian Test Symposium. He also served on the editorial boards of several journals, including IEEE Design and Test, and on the Steering and Program Committees of many of the major IEEE international test and design automation conferences. He served two terms (2007-11) as Chair of the IEEE Test Technology Technical Council (TTTC), and (2011-15) on the Board of Governors of the IEEE Council on Design Automation (CEDA). Professor Singh was elected Fellow of IEEE in 2002. He is Golden Core member of the IEEE Computer Society.

Tutorial 2:

ENHANCING TRUSTWORTHINESS IN THE GLOBAL IC SUPPLY CHAIN

Giorgio DI NATALE (TIMA - CNRS / Université Grenoble-Alpes / Grenoble INP) 

In the current global landscape of Integrated Circuits (ICs) supply chain, which now includes the emerging 3D and chiplet-based circuits, the importance of security and reliability in manufactured circuits cannot be overstated. This tutorial is designed to offer a thorough comprehension of these issues and investigate possible strategies to address them in both traditional 2D and emerging 3D/chiplet-based ICs. The tutorial will kick off with a broad look at the present condition of the global ICs supply chain, pointing out the main weaknesses that could be taken advantage of by ill-intentioned parties. We will thoroughly examine various types of IC piracy, such as hardware Trojans, counterfeiting, and reverse engineering, and consider their potential consequences for the industry. As we progress in the tutorial, we will concentrate on hardware authentication and metering techniques. These approaches play a vital role in verifying the genuineness of ICs and curbing overproduction. We will go over the existing studies on hardware authentication, covering Physical Unclonable Functions (PUFs), and IC metering methods like logic locking. Wrapping up the tutorial, we will engage in a conversation about the forthcoming research directions in IC security, shedding light on the prospective obstacles and prospects in this domain. Attendees will acquire a well-rounded understanding of the risks and potential remedies in the global ICs supply chain, empowering them to make valuable contributions to this essential research area.

Giorgio Di Natale received the PhD in Computer Engineering from the Politecnico di Torino in 2003. He works as Director of Research for the French National Research Center (CNRS), and he is the director of the TIMA laboratory in Grenoble since January 2021. His research interests include hardware security and trust, secure circuits design and test, reliability evaluation and fault tolerance, and VLSI testing. He has published 2 books and 9 book chapters, 50+ journal papers, and more than 150 conference and symposium papers in these domains. He has been involved in projects funded by the EU, Italy and France. He has been the action chair of the COST Action TRUDEVICE (Trustworthy Manufacturing and Utilization of Secure Devices), the biggest European research network on hardware security and trust. He also actively contributed in the organization of the main international conferences in his domain (general chair of DATE20, program chair of DATE17, steering committee member of ETS, program chair of ETS16, member of organizing committee of ETS and VTS since 2010). He belongs to the program committees of many conferences (DATE, ETS, IOLTS, DSD, DTIS, FDTC, GLSVLSI, HOST, CS2) and he serves as associate editor for IEEE Transactions on CAD and IEEE Transactions on Computers. He served as chair of the IEEE Computer Society TTTC, he is Golden Core member of the Computer Society and Senior member of the IEEE.

Tutorial 3:

HIERARCHICAL AND TILE BASED DFT TECHNIQUES FOR AI AND LARGE SOC

Lee HARRISON (Siemens EDA) 

In this tutorial, we will proceed to give an overview of the exciting field of AI and HPC. It will cover the critical and special characteristics and the architecture of the popular AI chips. Next we will summarize the features of the AI chips from design-for-test (DFT) perspective and introduce the DFT technologies that can help testing AI chips. We will also look at how the shift to 2.5D and 3D including Chiplet development is changing the industry and the adding new challenges for the DFT community Finally, we will present a few case studies on how DFT is implemented in the real AI chips. We will also present some of the functional monitoring techniques that are available today. An overall architecture showing how functional monitoring can be implemented and how the monitor data can be used to manage in-life capabilities. Finally, we will present a few case studies on how DFT is implemented in the real AI chips.

Lee Harrison is Product Marketing Director, with the Tessent product division at Siemens EDA. He has over 20 years of industry experience with Mentor DFT products and has been involved in the specification of new test features and methodologies for Mentor customers, delivering high quality DFT solutions. With a focus on Automotive, Lee is working to ensure that current and future DFT requirements of Mentor’s Automotive customers are understood and met. Lee Received his BEng in MicroElectronic Engineering from Brunel University London in 1996. Lee presents regularly at industry conferences such as DAC, ITC, VTS, ETS, DATE etc.

Tutorial 4:

LLM-ASSISTED ANALYTICS IN SEMICONDUCTOR TEST

Li-C. WANG (UC Santa Barbara) 

The emerge of Large Language Model (LLM) have significantly impacted our view for applying Machine Learning (ML) in semiconductor test. Recent LLMs include Codex focusing on code generation and InstructGPT for capturing user intent. Their successor, ChatGPT, had demonstrated remarkable performance for engaging in dialog on a wide variety of topics, answering questions, and generating code. With these recent LLM technological developments, this tutorial provides an integrated view of how to apply LLM in semiconductor test data analytics. In particular, we will cover introductory materials for LLMs and share our experience of leveraging the power of LLMs to build an AI Agent in semiconductor test domain. We will discuss a new paradigm called Decision-Support ML (DSML). In our domain, DSML is applied in an iterative exploration process for an engineer to learning knowledge from data. We will discuss common test data analytics practices as well as the latest LLM technologies and how they fit into our DSML view to build an end-to-end LLM-Assisted AI solution. Industrial case studies will be provided to illustrate the concepts taught in this tutorial.

Li-C. Wang is a professor at ECE department at University of CA, Santa Barbara. He received PhD in 1996 from University of Texas, Austin, and was previously with Motorola PowerPC Design Center. Starting from 2003, his research has focused on investigating how machine learning could be utilized in design and test flows, where he had published more than 100 papers and supervised 22 PhD theses on the related subjects. Prior to that, his research spanned across multiple topics in EDA and test, including microprocessor test and verification, statistical timing analysis, defect-oriented testing, and SAT solvers. He received 9 Best Paper Awards and 2 Honorable Mentioned Paper Awards from major conferences, including recent best paper awards from ITC 2020, ITC 2014, VTS 2016, and VLSI-DAT 2019. He is the recipient of the 2010 Technical Excellence Award from Semiconductor Research Corporation (SRC) for his research contributions in data mining for test and validation. He is the recipient of the 2017 IEEE-TTTC Bob Madge Innovation Award. He is an IEEE fellow and serve as the General Chair of the International Test Conference (ITC) in 2017, 2018, and 2023.

Tutorial 5:

AUTOMOTIVE FUNCTIONAL SAFETY USING PREDICTIVE MAINTENANCE

Yervant ZORIAN, Jyotika ATHAVALE (Synopsys) 

This tutorial will cover safety critical automotive systems with the usage of predictive maintenance. This will include current technology trends for silicon health in the context of automotive use cases. To address the challenges and risks associated with advanced SOC technologies in the context of automotive functional safety, there has been a growing effort recently in the development of new methods, practices and standards for dependable computing. This tutorial will discuss these new topics, including the revised ISO 26262, IEEE P2851 and several other recent international standardization efforts in the area of silicon health and automotive functional safety. In addition, the tutorial will highlight the significance of Silicon Lifecycle Management (SLM) technologies in enhancing functional safety and addressing the associated challenges.

Dr. Zorian is a Chief Architect and Fellow at Synopsys, as well as President of Synopsys Armenia. Formerly, he was Vice President and Chief Scientist of Virage Logic, Chief Technologist at LogicVision, and a Distinguished Member of Technical Staff AT&T Bell Laboratories. He is currently the President of IEEE Test Technology Technical Council (TTTC), the founder and chair of the IEEE 1500 Standardization Working Group, the Editor-in-Chief Emeritus of the IEEE Design and Test of Computers and an Adjunct Professor at University of British Columbia. He served on the Board of Governors of Computer Society and CEDA, was the Vice President of IEEE Computer Society, and the General Chair of the 50th Design Automation Conference (DAC) and several other symposia and workshops. Dr. Zorian holds 35 US patents, has authored four books, published over 350 refereed papers and received numerous best paper awards. A Fellow of the IEEE since 1999, Dr. Zorian was the 2005 recipient of the prestigious Industrial Pioneer Award for his contribution to BIST, and the 2006 recipient of the IEEE Hans Karlsson Award for diplomacy. He received the IEEE Distinguished Services Award for leading the TTTC, the IEEE Meritorious Award for outstanding contributions to EDA, and in 2014, the Republic of Armenia's National Medal of Science. He received an MS degree in Computer Engineering from University of Southern California, a PhD in Electrical Engineering from McGill University, and an MBA from Wharton School of Business, University of Pennsylvania.

Jyotika Athavale is a Director, Engineering Architecture at Synopsys, leading quality, reliability and safety research, pathfinding and architectures for data centers and automotive applications. She also serves as the 2024 President of the IEEE Computer Society, overseeing overall IEEE-CS programs, operations and service to the global computing community. Jyotika led the development of the IEEE 2851-2023 standard on Functional Safety Data Format for Interoperability, and now chairs the IEEE P2851.1 standardization initiative on Functional Safety interoperability with reliability. For her leadership in international safety standardization, Jyotika was awarded the 2023 IEEE SA Standards Medallion. And for her leadership in service, she was awarded the IEEE Computer Society Golden Core Award in 2022. Jyotika has authored patents and many technical publications in various international conferences and journals. She has also pioneered and chaired international workshops and conferences in the field of dependable technologies.

Tutorial 6:

MIXED-SIGNAL DFT CHALLENGES AND SOLUTIONS

Stephen SUNTER (Siemens EDA) 

This tutorial explores systematic analog and mixed-signal design-for-test, including analog fault/defect simulation. We review widely-used basic DfT techniques, fault simulation, IEEE 1149.1/4/6/7, 1687, and ISO 26262 metrics, then BIST for ADC/DAC, PLL, SerDes/DDR, and random analog. Essential principles of practical analog BIST are presented, then practical DfT techniques, from quicker analog defect simulation, to DfT that focuses on simplicity, diagnosis, reuse, and automation. We conclude with a detailed summary of the Analog Defect Coverage and Analog Test Access standards (IEEE P1687.2, P2427), as they approach completion thanks to the effort of dozens of people over many years.

Steve graduated from the University of Waterloo in 1978 with a Bachelor of Applied Science in Electrical Engineering. He worked in mixed-signal IC design from 1977 to 1990 at Bell-Northern Research and Nortel, in Canada. In Australia, he developed digital DfT and ATPG solutions at GEC-Plessey Telecommunications from 1990 to 1992, then in Canada he managed mixedsignal test engineering at Nortel until 1995 (many years before Nortel’s demise). In 1996, he became Engineering Director of mixed-signal DfT at LogicVision, which was acquired by Mentor Graphics in 2009, then by Siemens in 2017, where he continues to hold that position. During his 45+ years in mixed-signal IC design, DfT, and test, in addition to being granted 30 U.S. patents, Steve has published over 60 journal/conference papers on mixed-signal DfT/BIST topics, four of which won ITC Best Paper or Honorable Mention awards (the most for a primary author). He has contributed chapters to four books about mixed-signal DfT and BIST, one of which was described in an IEEE Design & Test review as, “a model of how a tutorial chapter should be written.” He has presented tutorials more than 30 times, to audiences of 20~120, most lasting a half day, and written articles in magazines such as EDN, Evaluation Engineering, and Computer Design. He is/was an active member of the Working Groups for all IEEE mixed-signal DfT-related standards: 1149.4, .6, .8, and .10, he chaired the P2427 Working Group for many years and is presently Chair of the P1687.2 WG. He served on the Program Committees of ITC and VTS for over 15 years, the Program Committees for ETS, TTEP, TVHSAC, and DATE, and thrice as Program Chair/Co-Chair for the International Mixed Signals Testing Workshop (IMSTW). He is a Life Senior Member of IEEE and an Associate Editor of JETTA

Tutorial 7:

3DIC ADVANCED PACKAGING, TEST & SLM

Sandeep GOEL (TSMC), Yervant ZORIAN (Synopsys) 

Advancements in process technology have enabled the creation of chips with billions of transistors, significantly enhancing power and performance for high-performance computing (HPC) and AI applications. This complexity has spurred the development of various 3D integration and packaging techniques utilizing multi-die/chiplet-based designs. Advanced 3D integration technologies allow for the construction of multi-die systems, each offering specific advantages and trade-offs in terms of performance, application, and cost. Similar to traditional chips, all 3DICs must be rigorously tested for manufacturing defects. This includes Known-Good Die (KGD) testing before stacking, Known-Good-Stack (KGS) testing after stacking, final tests, and system-level tests. Furthermore, given the complexity of the stacking process, in-silicon monitoring solutions are necessary to continuously check silicon health during in-field operation. This tutorial offers an overview of the advanced packaging technologies and explores the associated test flow challenges. An example of how the 3Dblox open standard simplifies the description of a 3D stack, enabling interoperability between EDA tools and allowing various test optimizations, is presented. Additionally, it covers various Design-for-Test (DFT) schemes, sensors/monitors and embedded test & repair solutions to facilitate efficient testing across different packaging configurations.

Tutorial 8:

ARTIFICIAL INTELLIGENCE SAFETY

Annachiara RUOSPO (Politecnico di Torino), Riccardo MARIANI (NVIDIA) 

Artificial Intelligence is today a rapidly evolving science that envisions the creation of intelligent machines capable of delivering numerous economic and social benefits. For its several qualities, AI can provide competitive advantages to companies and, in general, to the society. However, the widespread use of AI-based systems has raised some concerns about their deployment in safety-critical systems. This tutorial will introduce background concepts about dependability of complex systems, deep learning, and will provide an overview of the main hardware architectures adopted to run AI algorithms, i.e., GPUs, ASICs, TPUs, HW accelerators. Emphasis will be placed on the AI Safety standardization landscape: some of the main international industry standards will be outlined. It will be described in detail the status of AI safety standardization, in particular the content of ISO IEC TR 5469 (“Artificial intelligence - Functional safety and AI systems”). Few use cases will be presented and discussed. Next, the tutorial will present the most representative methodologies proposed to assess and increase the safety level of modern systems. The tutorial will mainly tackle, but will be not limited to, fault injection-based approaches at the software level, architectural level, and physical level (e.g., radiation tests). Next, fault mitigation and fault detection approaches (e.g., software test libraries, image test libraries) will be presented. To conclude, the tutorial will discuss future trends and challenges.

Annachiara Ruospo is an Assistant Professor in the Department of Control and Computer Engineering at Politecnico di Torino, Italy. She received her M.Sc. in Computer Engineering in 2018, completing her master’s thesis at ETH Zurich in 2017. She received her Ph.D. in Control and Computing Engineering, cum laude, from Politecnico di Torino in 2022. During her Ph.D., she was a Visiting Ph.D. Student at the Ecole Centrale de Lyon, France, where she focused on the reliability of deep learning applications. Her primary research interests include the safety, reliability, and security of AI systems, with a particular emphasis on artificial neural networks and the testing and verification of modern embedded devices. She is a member of the AI Existential Safety Community at the Future of Life Institute.

Riccardo Mariani is widely recognized as an expert in functional safety and integrated circuit reliability. In his current role as chief functional safety technologist at Intel Corporation, he oversees strategies and technologies for IoT applications that require functional safety, high reliability and performance, such as autonomous driving, transportation and industrial systems. Mariani spent the bulk of his career as CTO of Yogitech, an industry leader in functional safety technologies. Before co-founding the Italian company in 2000, he was technical director at Aurelia Microelettronica, where his responsibilities included leading high-reliability topics in projects with CERN in Geneva. A prolific author and respected inventor in the functional safety field, Mariani has contributed to multiple industry standards efforts throughout his career, including leading the ISO 26262-11 part specific to semiconductors. He has also won the SGS-Thomson Award and the Enrico Denoth Award for his engineering achievements. He holds a bachelor's degree in electronic engineering and a Ph.D. in microelectronics from the University of Pisa in Italy.

Tutorial 9:

FUNCTIONAL TESTING TECHNIQUES

Paolo BERNARDI (Politecnico di Torino) 

Since the inception of IC design in the mid-1960s, IC test has been an integral part of the manufacturing process. Initially, tests were of the Functional nature of either randomly generated or created from verification suites. But as chips got larger, testing required a more targeted approach, one that needed to be easily replicated from one design to another. This led to the invention of Structural methods like scan, which made designs combinational and simplified the test generation process. After almost 50 years, the testing scenario evolved just slightly, following technology trends currently led by the complexity of the circuits under test and the field of use (i.e., Automotive). Structural methods are still dominant, at least during the manufacturing test process, but Functional techniques are now recognized to be: (i) Useful to complement structural techniques during the manufacturing test process, such as System Level Test. (ii) Able to mitigate thermal issues that may originate during stress phases like along Burn-In, thus enabling test data collection during this phase. (iii) Very helpful along with the useful life of the components in the mission field, to run a not destructive self-test and also able to capture and store information, opening possibilities for Silicon Lifetime Management (SLM). The talk will provide basic and practical information about some today-relevant functional techniques in the field of Software-Based Self-Test (SBST), Burn-In Functional Stress/Test (TDBI), and System-Level Test (SLT). Automotive chip case studies from STMicroelectronics will be illustrated.

Paolo Bernardi (MS'02 and PhD'06 in Computer Science) is an Associate Professor of the Politecnico di Torino University, working in the Electronic CAD and Reliability research group. His current interests include System-on-Chip test and reliability, especially in the direction of high-quality automotive devices. Prof. Bernardi is the General Chair of the European Test Symposium 2023 (ETS23) and the Program Chair of the Automotive Reliability and Test (ART) Workshop held in conjunction with the International Test Conference. He is an IEEE senior member.

Tutorial 10:

UCIE 2.0 BASED MULTI-CHIPLETS DESIGN & TEST

Debendra DAS SHARMA (Intel), Yervant ZORIAN (Synopsys) 

High-performance and power efficiency needs of emerging workloads demand on-package integration of heterogeneous processing units, memory, and electrical and optical interconnects. Applications such as artificial intelligence/machine learning, data analytics, 5G, automotive, and high-performance computing are driving these demands to meet the needs of cloud computing, intelligent edge, enterprise, client, and hand-held computing infrastructure. On-package interconnects are a critical component to deliver the power-efficient performance with the right feature set in this evolving landscape.

UCIe is an open industry standard with a fully specified stack that comprehends plug-and-play interoperability of chiplets on a package; like the seamless interoperability on board with well-established and successful off-package interconnect standards such PCI Express®, Universal Serial Bus (USB)®, and Compute Express Link (CXL)®. Recently, UCIe added significant enhancements for the test and debug infrastructure to work seamlessly across the silicon life cycle. In this tutorial, we will discuss the usages and key metrics of UCIe, both planar as well as 3D. We will delve into electrical, packaging, protocol, RAS, debug, testability, manageability, and software aspects along with the compliance and interoperability mechanisms. This will address inter die and intra die requirements. The intended audience of this tutorial are architects, SoC developers, chip designers, DFT & test engineers, researchers, and system integrators.

Tutorial 11:

COMPUTATION IN MEMORY: TECHNOLOGIES, DESIGN, TEST AND RELIABILITY

Mehdi TAHOORI (Karlsruhe Institute of Technology) 

Computation-in-Memory (CiM) paradigms are providing promising alternatives to tackle memory wall and power wall. CiM architectures based on emerging resistive non-volatile technologies are finding their way to efficiently implement deep learning cognitive tasks. Such technologies combine the storage and computation capabilities into the single device based on analog computing concepts. While many emerging technologies are being investigated for efficient implementation of such architectures and paradigms, there are several challenges related to test and reliability aspects of these technologies and architectures. From one side, these emerging devices are more prone to variations and defects, and from the other side, CiM paradigms crosses computation and storage boundaries, which were considered separated in traditional design-for-test (DfT) and design-for-reliability (DfR) solutions. This tutorial addresses design, test and reliability aspects of CiM technologies, circuits and architectures.

Mehdi Tahoori is Professor and the Chair of Dependable Nano-Computing at Karlsruhe Institute of Technology, Germany. He received the B.S. degree in computer engineering from Sharif University of Technology, Tehran, Iran, in 2000, and the M.S. and Ph.D. degrees in electrical engineering from Stanford University, Stanford, CA, in 2002 and 2003, respectively. In 2003, he was an Assistant Professor with the Department of Electrical and Computer Engineering, Northeastern University, where he became an Associate Professor in 2009. He was a visiting professor at VLSI Design and Education Center (VDEC), University of Tokyo, Japan in 2015. From 2002 to 2003, he was a Research Scientist with Fujitsu Laboratories of America, Sunnyvale, CA. He has authored over 400 publications in major journals and conference proceedings on a wide range of topics, from dependable computing and emerging nanotechnologies to system biology, and holds several US and European patents. He is currently the deputy editor-in-chief of IEEE Design and Test Magazine. He was the editor-in-chief of Microelectronic Reliability journal. He was the program chair of VLSI Test Symposium in 2021 and was General Chair of European Test Symposium in 2019. Prof. Tahoori was a recipient of the National Science Foundation Early Faculty Development Award. He has received a number of best paper nominations and awards at various conferences and journals. He is a fellow of IEEE.

Tutorial 12:

IN-FIELD SYSTEM TEST & DEBUG

Amit PANDEY (Amazon), Karthik NATARJAN (Synopsys), Sankaran MENON (Ericsson) 

Infield Test and Debug provides deeper insights into the system behavior and structural quality while the system is running in mission-mode. It provides a non-intrusive method for testing and debug of complex computer systems. This is specifically useful in mission-critical applications such as; space applications, ADAS (Advanced Driver Assistance Systems), for various industrial/robotic applications as well as virtually all real-time and data-center/AI applications. In this tutorial we will establish the motivation for Infield system Test & Debug, cover the various testing and debug techniques that are available today. We will then introduce the Infield system testing and debug mechanisms available for the closed-chassis systems using USB Type-C, PCIe and any other high-speed interfaces. We will conclude with results from an Infield system test and Debug used in real-world applications across the various industries.