LLM-Power AI Agents for Semiconductor Test

Li-C. Wang (UC Santa Barbara) 

The emerge of Large Language Model (LLM) have significantly impacted our view for applying Machine Learning (ML) in semiconductor test. Recent LLMs include Codex focusing on code generation and InstructGPT for capturing user intent. Their successor, ChatGPT, had demonstrated remarkable performance for engaging in dialog on a wide variety of topics, answering questions, and generating code. With these recent LLM technological developments, this tutorial provides an integrated view of how to apply LLM in semiconductor test data analytics. In particular, we will cover introductory materials for LLMs and share our experience of leveraging the power of LLMs to build an AI Agent in semiconductor test domain. We will discuss a new paradigm called Decision-Support ML (DSML). In our domain, DSML is applied in an iterative exploration process for an engineer to learning knowledge from data. We will discuss common test data analytics practices as well as the latest LLM technologies and how they fit into our DSML view to build an end-to-end LLM-Assisted AI solution. Industrial case studies will be provided to illustrate the concepts taught in this tutorial.

Li-C. Wang is a professor at ECE department at University of CA, Santa Barbara. He received PhD in 1996 from University of Texas, Austin, and was previously with Motorola PowerPC Design Center. Starting from 2003, his research has focused on investigating how machine learning could be utilized in design and test flows, where he had published more than 100 papers and supervised 22 PhD theses on the related subjects. Prior to that, his research spanned across multiple topics in EDA and test, including microprocessor test and verification, statistical timing analysis, defect-oriented testing, and SAT solvers. He received 9 Best Paper Awards and 2 Honorable Mentioned Paper Awards from major conferences, including recent best paper awards from ITC 2020, ITC 2014, VTS 2016, and VLSI-DAT 2019. He is the recipient of the 2010 Technical Excellence Award from Semiconductor Research Corporation (SRC) for his research contributions in data mining for test and validation. He is the recipient of the 2017 IEEE-TTTC Bob Madge Innovation Award. He is an IEEE fellow and serve as the General Chair of the International Test Conference (ITC) in 2017, 2018, and 2023.

CAD for SoC Security

Mark Tehranipoor (University of Florida), Farimah Farahmandi (University of Florida) 

Hierarchical and tile based DFT techniques for AI and Large SoC

Lee Harrison (Siemens EDA), Peter Orlando (Siemens EDA) 

In this tutorial, we will proceed to give an overview of the exciting field of AI and HPC. It will cover the critical and special characteristics and the architecture of the popular AI chips. Next we will summarize the features of the AI chips from design-for-test (DFT) perspective and introduce the DFT technologies that can help testing AI chips. We will also look at how the shift to 2.5D and 3D including Chiplet development is changing the industry and the adding new challenges for the DFT community Finally, we will present a few case studies on how DFT is implemented in the real AI chips. We will also present some of the functional monitoring techniques that are available today. An overall architecture showing how functional monitoring can be implemented and how the monitor data can be used to manage in-life capabilities. Finally, we will present a few case studies on how DFT is implemented in the real AI chips.

Lee Harrison is Product Marketing Director, with the Tessent product division at Siemens EDA. He has over 20 years of industry experience with Mentor DFT products and has been involved in the specification of new test features and methodologies for Mentor customers, delivering high quality DFT solutions. With a focus on Automotive, Lee is working to ensure that current and future DFT requirements of Mentor’s Automotive customers are understood and met. Lee Received his BEng in MicroElectronic Engineering from Brunel University London in 1996. Lee presents regularly at industry conferences such as DAC, ITC, VTS, ETS, DATE etc.

System Level Test Techniques

Paolo Bernardi (Politecnico di Torino) 

Since the inception of IC design in the mid-1960s, IC test has been an integral part of the manufacturing process. Initially, tests were of the Functional nature of either randomly generated or created from verification suites. But as chips got larger, testing required a more targeted approach, one that needed to be easily replicated from one design to another. This led to the invention of Structural methods like scan, which made designs combinational and simplified the test generation process. After almost 50 years, the testing scenario evolved just slightly, following technology trends currently led by the complexity of the circuits under test and the field of use (i.e., Automotive). Structural methods are still dominant, at least during the manufacturing test process, but Functional techniques are now recognized to be: (i) Useful to complement structural techniques during the manufacturing test process, such as System Level Test. (ii) Able to mitigate thermal issues that may originate during stress phases like along Burn-In, thus enabling test data collection during this phase. (iii) Very helpful along with the useful life of the components in the mission field, to run a not destructive self-test and also able to capture and store information, opening possibilities for Silicon Lifetime Management (SLM). The talk will provide basic and practical information about some today-relevant functional techniques in the field of Software-Based Self-Test (SBST), Burn-In Functional Stress/Test (TDBI), and System-Level Test (SLT). Automotive chip case studies from STMicroelectronics will be illustrated.

Paolo Bernardi (MS'02 and PhD'06 in Computer Science) is an Associate Professor of the Politecnico di Torino University, working in the Electronic CAD and Reliability research group. His current interests include System-on-Chip test and reliability, especially in the direction of high-quality automotive devices. Prof. Bernardi is the General Chair of the European Test Symposium 2023 (ETS23) and the Program Chair of the Automotive Reliability and Test (ART) Workshop held in conjunction with the International Test Conference. He is an IEEE senior member.

Industry RAS/SDC Innovative Practices: from Si IP to Mega Fleets

Drew Walton (Microsoft), Yogesh Varma (Intel) 

Mixed-Signal DfT Challenges and Solutions

Stephen Sunter (Siemens EDA) 

This tutorial explores systematic analog and mixed-signal design-for-test, including analog fault/defect simulation. We will review widely-used basic DfT techniques, fault simulation, IEEE 1149.1/4/6/7, 1687, and ISO 26262 metrics, then BIST for ADC/DAC, PLL, SerDes/DDR, and random analog. Essential principles of practical analog BIST are presented, then practical DfT techniques, from quicker analog defect simulation, to DfT that emphasizes simplicity, diagnosis, reuse, and automation. Detailed summaries of the Analog Defect Coverage and Analog Test Access standards (IEEE P2427, P1687.2) are included, as they approach completion thanks to the effort of many people since 2014. The tutorial concludes with an introduction to digital scan-based DfT that enables ATPG for near-instantaneous high-coverage structural testing of analog circuits.

Steve graduated from the University of Waterloo in 1978 with a Bachelor of Applied Science in Electrical Engineering. He designed mixed-signal ICs from 1977 to 1990 at Bell-Northern Research and Nortel, in Canada. In Australia, he developed digital DfT and ATPG solutions at GEC-Plessey Telecommunications from 1990 to 1992, then in Canada he managed mixed-signal test engineering at Nortel until 1995 (years before Nortel’s demise). In 1996, he became Engineering Director of mixed-signal DfT at LogicVision, which was acquired by Mentor Graphics in 2009, then by Siemens in 2017, where he continues to hold that position. During his 45+ years in mixed-signal IC design, DfT, and test, in addition to being granted 30 U.S. patents, Steve is the primary author of over 60 journal/conference papers on mixed-signal DfT/BIST topics, four of which won ITC Best Paper or Honorable Mention awards (the most for a primary author). He has contributed chapters to four books about mixed-signal DfT and BIST, one of which was described in an IEEE Design & Test review as, “a model of how a tutorial chapter should be written.” He has presented tutorials over 30 times, to audiences of 20~120, most lasting a half day, and written articles in magazines such as EDN, Evaluation Engineering, and Computer Design. He is/was an active member of the Working Groups for all IEEE mixed-signal DfT-related standards (1149.4, .6, .8, and .10), he chaired the P2427 Working Group for many years, and is presently Chair of the P1687.2 WG. He served on the Program Committees of ITC and VTS for over 15 years, the Program Committees for ETS, TTEP, TVHSAC, and DATE, and thrice as Program Chair/Co-Chair for the International Mixed Signals Testing Workshop (IMSTW). He is a Life Senior Member of IEEE and an Associate Editor of JETTA.

3DIC Advanced Packaging, Test & SLM

Sandeep Goel (TSMC), Yervant Zorian (Synopsys) 

Advancements in process technology have enabled the creation of chips with billions of transistors, significantly enhancing power and performance for high-performance computing (HPC) and AI applications. This complexity has spurred the development of various 3D integration and packaging techniques utilizing multi-die/chiplet-based designs. Advanced 3D integration technologies allow for the construction of multi-die systems, each offering specific advantages and trade-offs in terms of performance, application, and cost. Similar to traditional chips, all 3DICs must be rigorously tested for manufacturing defects. This includes Known-Good Die (KGD) testing before stacking, Known-Good-Stack (KGS) testing after stacking, final tests, and system-level tests. Furthermore, given the complexity of the stacking process, in-silicon monitoring solutions are necessary to continuously check silicon health during in-field operation. This tutorial offers an overview of the advanced packaging technologies and explores the associated test flow challenges. An example of how the 3Dblox open standard simplifies the description of a 3D stack, enabling interoperability between EDA tools and allowing various test optimizations, is presented. Additionally, it covers various Design-for-Test (DFT) schemes, sensors/monitors and embedded test & repair solutions to facilitate efficient testing across different packaging configurations.

Dr. Zorian is a Chief Architect and Fellow at Synopsys, as well as President of Synopsys Armenia. Formerly, he was Vice President and Chief Scientist of Virage Logic, Chief Technologist at LogicVision, and a Distinguished Member of Technical Staff AT&T Bell Laboratories. He is currently the President of IEEE Test Technology Technical Council (TTTC), the founder and chair of the IEEE 1500 Standardization Working Group, the Editor-in-Chief Emeritus of the IEEE Design and Test of Computers and an Adjunct Professor at University of British Columbia. He served on the Board of Governors of Computer Society and CEDA, was the Vice President of IEEE Computer Society, and the General Chair of the 50th Design Automation Conference (DAC) and several other symposia and workshops. Dr. Zorian holds 35 US patents, has authored four books, published over 350 refereed papers and received numerous best paper awards. A Fellow of the IEEE since 1999, Dr. Zorian was the 2005 recipient of the prestigious Industrial Pioneer Award for his contribution to BIST, and the 2006 recipient of the IEEE Hans Karlsson Award for diplomacy. He received the IEEE Distinguished Services Award for leading the TTTC, the IEEE Meritorious Award for outstanding contributions to EDA, and in 2014, the Republic of Armenia's National Medal of Science. He received an MS degree in Computer Engineering from University of Southern California, a PhD in Electrical Engineering from McGill University, and an MBA from Wharton School of Business, University of Pennsylvania.

Timing Tests, Process Variations, Circuit Marginalities and Silent Data Corruption

Adit Singh (Auburn University) 

New types of failures that evade traditional scan DFT tests are increasingly observed in advanced SoC designs. Recent reports from Google and Meta have highlighted significant levels of silent data corruption in large-scale data centers. These failures have been associated with specific processor cores in the processor networks, suggesting faulty or unstable hardware, rather than malfunction caused by random environmental noise. Although the limitations of structural scan tests have led to the growing adoption of System-Level Tests (SLT) as a final manufacturing screen in recent years, even these expensive functional tests allow significant test escapes that can cause failures during operation. We argue that timing marginalities, caused by manufacturing process variations, are a primary contributor to both SLT fallout and in-field failures. To support this claim, we first review existing scan-based timing tests, including recent developments in cell-aware and timing-aware methodologies, highlighting their capabilities and limitations. We then explain why these tests often fail to detect timing-related defects from process variation. Finally, we present research—validated using production test data from Intel’s 14nm FinFET technology—that demonstrates how modifying voltage and timing conditions during scan and system-level testing can improve detection of circuits with marginal timing and thereby minimize failures in operation.

Dr. Adit D. Singh is Godbold Endowed Chair Professor of Electrical and Computer Engineering at Auburn University. Before joining Auburn in 1991, he served on the faculty at the University of Massachusetts in Amherst, and Virginia Tech in Blacksburg. He has held several visiting positions during sabbaticals, including at the University of Tokyo in Japan, the Universities of Freiburg and Potsdam in Germany, the Indian Institutes of Technology, and as Fulbright Awardee at the University Polytechnic of Catalonia in Barcelona, Spain. He has also conducted over 100 tutorials and short courses at conferences, universities and industry worldwide. His technical interests span all aspects of VLSI technology, in particular integrated circuit test and reliability. He has published over two hundred and fifty research papers and holds international patents that have been licensed to industry. He has had leadership roles as General Chair/Co-Chair/Program Chair for dozens of international VLSI design and test conferences. He also served on the editorial boards of several journals, including IEEE Design and Test, and on the Steering and Program Committees of many of the major IEEE international test and design automation conferences. He served two terms (2007-11) as Chair of the IEEE Test Technology Technical Council (TTTC), and (2011-15) on the Board of Governors of the IEEE Council on Design Automation (CEDA). Professor Singh was elected Fellow of IEEE in 2002. He is Golden Core member of the IEEE Computer Society.

Silent Data Corruption in AI Data Centers: Impact and Mitigation Strategies

Arani Sinha (Intel), Alberto Bosio (Ecole Centrale de Lyon), Ernesto Sanchez (Politecnico di Torino) 

AI applications have become extremely popular in everyday life as well as in the industry, but at the same time their complexity requires dedicated hardware accelerators deployed in cloud-based Data Centers. Recent studies by hyperscalers have revealed that Data Center hardware can experience failures leading to Silent Data Corruption (SDC). SDCs can impact AI workloads both during training and inference and, eventually, cause huge revenue loss. The tutorial will start with an introduction to Silent Data Corruption. The tutorial will then offer an overview of the landscape of artificial intelligence, focusing on basic frameworks such as Multi Layer Perceptron, Deep Neural Networks, and Transformers. The following phase of the tutorial will focus on AI architectures such as Tensor Processing Unit from Google, Gaudi architecture from Intel, and GPU architecture from Nvidia. After that, the impact of manufacturing defects on training and inference will be discussed and fault injection techniques developed for studying the impact of defects will be described. Next, developments in functional and structural testing of AI architectures will be discussed. Finally, such resilience techniques as gradient clipping, algorithmic fault tolerance, and tensor processing monitor will be described. The tutorial will end with a brief discussion on open research problems in this space.

Arani Sinha is a Principal Engineer and a Design-For-Test (DFT) Lead in the datacenter design organization in Intel, Hillsboro, OR, USA. He has also worked for the Intel foundry and for AMD and Cadence. Arani has 20+ years of experience in DFT design, EDA tools development, physical design, and timing analysis. His research interests include advanced fault models, silent data corruption, reliability of AI architectures, and chiplet test. He served as the General Chair and Program Chair for the IEEE Workshop on Defects, Adaptive Test and Yield Analysis from 2012-2016. He was the Program Chair for VLSI Test Symposium, 2025. Arani received the Mahboob Khan award from Semiconductor Research Corporation in 2022 for mentoring Ph.D. students. He has co-presented tutorials on delay test at the Latin American Test Workshop (LATW) and International Test Conference (ITC), on speedpath validation at the European Test Symposium (ETS), and on post-silicon validation at the International Test Conference (ITC). He has co-authored 30+ publications in conferences and journals. Arani has a PhD degree in Electrical Engineering from the University of Southern California, Los Angeles. He is a Senior Member of IEEE and ACM.

Alberto Bosio has completed all his studies in Italy, including the Ph.D. in Computer Engineering in digital systems dependability at the Politecnico di Torino (Italy) in 2006. Since 2018 he is a Full Professor at the Ecole Centrale de Lyon Institute of Nanotechnology. His research focuses on the dependability of computing systems, the design and test of emerging computing architectures, and the approximate computing paradigm. He is the co-author of 4 books, four patents, 54 papers in international journals, and 164 articles in international conferences and workshops. He received several best paper awards in international conferences, including IEEE DFT 2020, IEEE DDECS 2016, and IEEE VTS 2016. He served as a committee and organizing member in several international conferences, He served as program chair of DDECS 2019 and DDECS 2020, ETS 2023 and Program chair of DATE 2026. He served as a steering committee member in DDECS. He was guest editor for IEEE D&T, ACM JETC, ELSEVIER Microelectronics & Reliability, ELSEVIER Future Generation Computer Systems, and World Scientific Journal of Circuits, Systems, and Computers. He is a member of the IEEE and the Co-Chair of the European Test Technical Technology Council (eTTTC).

Ernesto Sanchez is an Associate professor at Politecnico di Torino, Italy. His research interests include digital circuits and systems reliability, evolutionary computation, Hardware Security and ANN reliability. He received his Electronic Engineering degree from Universidad Javeriana, Colombia in 2000, and his Ph.D. degree in Computing Engineer from Politecnico di Torino, Italy in 2006. He is an IEEE senior member.

UCIe based Multi-Chiplets Design & Test

Debendra Das Sharma (Intel), Yervant Zorian (Synopsys) 

High-performance and power efficiency needs of emerging workloads demand on-package integration of heterogeneous processing units, memory, and electrical and optical interconnects. Applications such as artificial intelligence/machine learning, data analytics, 5G, automotive, and high-performance computing are driving these demands to meet the needs of cloud computing, intelligent edge, enterprise, client, and hand-held computing infrastructure. On-package interconnects are a critical component to deliver the power-efficient performance with the right feature set in this evolving landscape.

UCIe is an open industry standard with a fully specified stack that comprehends plug-and-play interoperability of chiplets on a package; like the seamless interoperability on board with well-established and successful off-package interconnect standards such PCI Express®, Universal Serial Bus (USB)®, and Compute Express Link (CXL)®. Recently, UCIe added significant enhancements for the test and debug infrastructure to work seamlessly across the silicon life cycle. In this tutorial, we will discuss the usages and key metrics of UCIe, both planar as well as 3D. We will delve into electrical, packaging, protocol, RAS, debug, testability, manageability, and software aspects along with the compliance and interoperability mechanisms. This will address inter die and intra die requirements. The intended audience of this tutorial are architects, SoC developers, chip designers, DFT & test engineers, researchers, and system integrators.

Dr. Zorian is a Chief Architect and Fellow at Synopsys, as well as President of Synopsys Armenia. Formerly, he was Vice President and Chief Scientist of Virage Logic, Chief Technologist at LogicVision, and a Distinguished Member of Technical Staff AT&T Bell Laboratories. He is currently the President of IEEE Test Technology Technical Council (TTTC), the founder and chair of the IEEE 1500 Standardization Working Group, the Editor-in-Chief Emeritus of the IEEE Design and Test of Computers and an Adjunct Professor at University of British Columbia. He served on the Board of Governors of Computer Society and CEDA, was the Vice President of IEEE Computer Society, and the General Chair of the 50th Design Automation Conference (DAC) and several other symposia and workshops. Dr. Zorian holds 35 US patents, has authored four books, published over 350 refereed papers and received numerous best paper awards. A Fellow of the IEEE since 1999, Dr. Zorian was the 2005 recipient of the prestigious Industrial Pioneer Award for his contribution to BIST, and the 2006 recipient of the IEEE Hans Karlsson Award for diplomacy. He received the IEEE Distinguished Services Award for leading the TTTC, the IEEE Meritorious Award for outstanding contributions to EDA, and in 2014, the Republic of Armenia's National Medal of Science. He received an MS degree in Computer Engineering from University of Southern California, a PhD in Electrical Engineering from McGill University, and an MBA from Wharton School of Business, University of Pennsylvania.

Design in Angestrom Era: Test, Reliability Challenges

Mehdi Tahoori (IMEC) 

Mehdi Tahoori is Professor and the Chair of Dependable Nano-Computing at Karlsruhe Institute of Technology, Germany. He received the B.S. degree in computer engineering from Sharif University of Technology, Tehran, Iran, in 2000, and the M.S. and Ph.D. degrees in electrical engineering from Stanford University, Stanford, CA, in 2002 and 2003, respectively. In 2003, he was an Assistant Professor with the Department of Electrical and Computer Engineering, Northeastern University, where he became an Associate Professor in 2009. He was a visiting professor at VLSI Design and Education Center (VDEC), University of Tokyo, Japan in 2015. From 2002 to 2003, he was a Research Scientist with Fujitsu Laboratories of America, Sunnyvale, CA. He has authored over 400 publications in major journals and conference proceedings on a wide range of topics, from dependable computing and emerging nanotechnologies to system biology, and holds several US and European patents. He is currently the deputy editor-in-chief of IEEE Design and Test Magazine. He was the editor-in-chief of Microelectronic Reliability journal. He was the program chair of VLSI Test Symposium in 2021 and was General Chair of European Test Symposium in 2019. Prof. Tahoori was a recipient of the National Science Foundation Early Faculty Development Award. He has received a number of best paper nominations and awards at various conferences and journals. He is a fellow of IEEE.

In-Field System Test & Debug

Amit Pandey (Amazon), Karthik Natarjan (Synopsys), Sankaran Menon (Ericsson) 

Infield Test and Debug provides deeper insights into the system behavior and structural quality while the system is running in mission-mode. It provides a non-intrusive method for testing and debug of complex computer systems. This is specifically useful in mission-critical applications such as; space applications, ADAS (Advanced Driver Assistance Systems), for various industrial/robotic applications as well as virtually all real-time and data-center/AI applications. In this tutorial we will establish the motivation for Infield system Test & Debug, cover the various testing and debug techniques that are available today. We will then introduce the Infield system testing and debug mechanisms available for the closed-chassis systems using USB Type-C, PCIe and any other high-speed interfaces. We will conclude with results from an Infield system test and Debug used in real-world applications across the various industries.